Design of AES Pipelined Architecture for Image Encryption/Decryption Module
نویسندگان
چکیده
منابع مشابه
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture
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ژورنال
عنوان ژورنال: International Journal of Reconfigurable and Embedded Systems (IJRES)
سال: 2014
ISSN: 2089-4864,2089-4864
DOI: 10.11591/ijres.v3.i3.pp114-118